library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity latched_34_adder is
	PORT (
	clk : in STD_LOGIC;
	input1 : in STD_LOGIC_VECTOR(34 downto 0);
	input2 : in STD_LOGIC_VECTOR(34 downto 0);
	
	output : out STD_LOGIC_VECTOR(34 downto 0) -- guaranteed to not exceed 
	);
end latched_34_adder;

architecture Behavioral of latched_34_adder is
begin
	process(clk)
	begin
		if (clk'event and clk='1') then
			output <= STD_LOGIC_VECTOR(unsigned(input1) + unsigned(input2));
		end if;	
	end process;
end Behavioral;

